Emulation/PreSi Val Engineer
Guadalajara, JAL, MX
hace 4 días

Job Description

In the Design Engineering Group, we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products.

From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.

As a member of the Intel Validation Engineering Group you’ll play an active role in validation and debug to ensure our products meet the highest quality standards before they reach our customer’s hands.

Creates emulation / Field Programmable Gate Array (FPGA) models from a Register Transfer Level (RTL) design using emulation / FPGA synthesis, partitioning and routing tools.

Defines and documents RTL changes required for emulation / FPGA.

Develops hardware and software collaterals and integrates it with the emulation / FPGA model.

Tests and debugs the emulation / FPGA model and collaterals.

Defines and develops new capabilities & HW / SW tools to enable acceleration of RTL and improve emulation / FPGA model usability for preSilicon and postSilicon functional validation as well as SW development / validation.

Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform.

Interfaces with and provides guidance to presilicon Validation teams for optimizing preSi validation environments, test suites and methodologies for emulation efficiency.

Develops and applies automation aids, flows and scripts in support of emulation easeofuse and improvement of equipment utilization.


Bachelor or Master Degree in Electronic Engineering or related fields.

Minimum Qualifications :

  • 1 years of Experience Intel Architecture, including CPU and PCH platforms
  • Computer architectures and interfaces (USB, UART, SPI, I2C, PCIe, ...)
  • 1 years of experience in one or more programming languages (C, C++, Python, Perl, Java)
  • Fundamentals in digital design
  • Preferred Qualifications :

  • Fundamentals in FPGA design flow
  • Hardware Description Languages (Verilog or VHDL)
  • Collaborative work skills
  • Combinational, Synchronous (state machines), Asynchronous
  • Communication skills (both in Spanish and English)
  • Experience in Power Management domain is a plus.
  • Experience using emulation platforms a plus (running / debugging tests, waveform capture)
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