Creates, defines and develops system validation environment and test suites. Cluster validation environment requires at scale debug capabilities and at scale telemetry management.
Responsible for the development of methodologies, execution of validation plans, and debug of failures. In addition knowledge on K8s and container environment are a plus.
Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Presilicon Validation teams in improving postsilicon test content and providing feedback for future ondie debug features.
A BS MS degree in Electrical / Electronic Engineer, Computer Science Engineer or similar engineering degree with at least 5 years of experience in product development or validation.
Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and providing feedback for future on-die debug features.
Skilled C / C++ / Python programmer.
Hardware debug capabilities using instruments, but not limited to Scope, Logic Analyzer or Protocol Analyzer
Digital Design knowledge (VHDL / Verilog is desired but not required).
Knowledge of Server and SoC platform architectures
Both written and spoken Fluid English communications.
Ability to self-organize and prioritize work.
Hunger for learning.