Creates emulation / Field Programmable Gate Array (FPGA) models from a Register Transfer Level (RTL) design using emulation / FPGA synthesis, partitioning and routing tools.
Defines and documents RTL changes required for emulation / FPGA.
Develops hardware and software collaterals and integrates it with the emulation / FPGA model.
Tests and debugs the emulation / FPGA model and collaterals.
Defines and develops new capabilities & HW / SW tools to enable acceleration of RTL and improve emulation / FPGA model usability for preSilicon and postSilicon functional validation as well as SW development / validation.
Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform.
Interfaces with and provides guidance to presilicon Validation teams for optimizing preSi validation environments, test suites and methodologies for emulation efficiency.
Develops and applies automation aids, flows and scripts in support of emulation easeofuse and improvement of equipment utilization.
Electronic, Electrical, Computer Engineering or related fields
Minimum Qualifications :
Preferred Qualifications :